In integrated circuits, wiring connects a plurality of electronic elements such as field effect transistors (FETs), capacitors, resistors and/or diodes to form functional electronic circuits. Typically, the electronic elements are arranged along a main surface of a semiconductor substrate such as a silicon wafer or a SoI (silicon-on-insulator) wafer. The wiring may be provided in several wiring layers, wherein interlevel dielectric layers are disposed between the wiring layers and between the bottom wiring layer and the main surface. Vertical contact structures (vias) connect wiring lines of different wiring layers with each other and with the electronic elements provided on or in the semiconductor substrate.
In some applications, each terminal of an electronic element, for example, a field effect transistor, may be connected to one or more of the wiring layers. Shrinking in size of the elements on the main surface results in dense contact arrangements. In order to relax overlay requirements and process windows, the contacts are conventionally arranged in a sufficient distance to each other such that the contact arrangement of an electronic element may consume more area than the electronic element itself. For example, the overall area of the contact arrangement of a 3D field effect transistor, which includes at least one channel section that is not oriented along a surface parallel to the main surface, like an EUD (extended U-groove device), a vertical field effect transistor, a recess channel transistor, or a FinFET, may be greater than the planar cross-section of the active area of the 3D field effect transistor.